orchis.ai · circuit simulation

Spic3y

An analog and mixed-signal circuit simulator, written from scratch in Rust. It reads the schematics you already have — KiCad projects, LTspice files, SPICE decks from your parts vendors — and it is checked against ngspice on every build.

Desktop downloads — coming soon

Loading the simulator in the background (about 10 MB, first visit only)…

What it does

Spic3y is a complete circuit simulator: you give it a circuit and it solves the nonlinear equations that describe it, in the time domain, the frequency domain, or at a single bias point. The solver is modified nodal analysis with a damped Newton iteration and an adaptive, error-controlled timestep — the same foundations as every SPICE since 1973, rewritten with modern tooling.

What distinguishes it is the front end. Most simulators expect you to keep a separate simulation schematic. Spic3y reads the design files you already have, resolves the manufacturer model libraries they point at, and tells you plainly when something in those files cannot be simulated and why.

Analyses

Operating point and DC

  • Bias point with node voltages and branch currents
  • DC sweeps, including nested two-source families for device curves
  • Small-signal transfer function: gain, input and output resistance

Frequency domain

  • AC sweeps, decade / octave / linear
  • Noise analysis by the adjoint method — thermal, shot, FET channel and flicker (1/f) contributions, with per-source breakdown
  • Fourier analysis of transient results, ten harmonics, checked against ngspice's .four, plus an FFT view with selectable windows (none, Hann, Hamming, Blackman–Harris)

Time domain

  • Transient with adaptive stepping under local-truncation-error control, backward-Euler start into trapezoidal; second-order Gear (BDF2) selectable with .options method=gear for stiff switching circuits, validated point-for-point against ngspice's own Gear
  • Start time, maximum timestep and use-initial-conditions all honored

Sweeps and statistics

  • Parameter, source and temperature sweeps (.step, .temp), overlaid as a curve family
  • Monte Carlo with uniform or Gaussian tolerances — including the ngspice-style gauss(nom,rvar,sigma) forms — reproducible per-sample random streams, and a histogram of measured results
  • Worst-case corner analysis over the same tolerances
  • Measurements (.meas): max, min, peak-to-peak, average, RMS, trigger/target timing, find-at, find-when

Device models

Passive and sources

  • Resistors with temperature coefficients and Johnson noise, capacitors, inductors, coupled inductors including multi-winding transformers
  • Independent sources: DC, AC, sine, pulse, piecewise-linear (with repeat and delay), exponential, single-frequency FM, amplitude modulation
  • Controlled sources E/G/F/H in every common dialect: linear, POLY, TABLE, VALUE=, LAPLACE transfer functions, and PSpice FREQ response tables
  • Behavioral sources with analytic Jacobians, including ddt() and idt() with exact small-signal derivatives

Semiconductors

  • Diodes: injection, series resistance, junction capacitance, transit time, reverse breakdown, temperature dependence
  • Bipolar transistors: transport model with forward and reverse Early effect, high-injection roll-off, leakage diodes and junction capacitances
  • MOSFETs and JFETs: level 1 square-law with region-dependent gate capacitance and body diodes
  • Power MOSFETs (VDMOS) with a two-slope gate–drain capacitance, quasi-saturation including its temperature dependence, and a body diode that models reverse recovery — transcribed from and checked against ngspice's implementation
  • Voltage- and current-controlled switches with true hysteresis; lossless transmission lines
  • Digital primitives — buffer, AND, OR, XOR, Schmitt trigger, SR and D flip-flops — and state machines, for mixed-signal work

Being specific, because it matters when you pick a tool: the built-in MOSFET is level 1. There is no BSIM, EKV or PSP compiled in. For short-channel process models the desktop application loads compiled Verilog-A modules through the OSDI interface, which is how you run BSIM-class models — you supply the compiled module.

Reading the files you already have

KiCad

  • Schematics and projects, KiCad 6 through 10, opened directly
  • Hierarchical sheets, vector and group buses, bus aliases
  • Multi-unit symbols merged into one device, so dual and quad op-amps simulate as the single physical part they are
  • Both the modern Sim.* fields and the legacy Spice_* ones, pin remapping, do-not-populate and exclude-from-simulation flags
  • Watch mode: save in KiCad, the simulation re-runs

LTspice, Verilog and vendor libraries

  • LTspice schematics and symbols, including custom symbols, hierarchical blocks and the digital device library
  • Structural Verilog netlists become simulatable subcircuits
  • Manufacturer model files in ngspice, LTspice, PSpice and HSPICE dialects: parameters and functions, conditional blocks, model inheritance, sectioned libraries
  • Encrypted vendor models are identified as such, with an explanation, instead of failing as a parse error

Editing and reading results

Schematic and netlist

  • Built-in schematic capture with around twenty part types, wiring, multi-select, copy and paste, rotate and mirror, undo and redo, and text annotations
  • Click a wire to probe a voltage, click a part to probe its current
  • Edits re-simulate automatically a moment after you stop typing
  • A readiness check that explains what is missing — floating nodes, no path to ground, absent models — before you hit a solver error

Waveforms

  • Stacked plot panes with a shared axis, and per-trace assignment between panes
  • A and B cursors with per-trace values and deltas
  • Trace math over the results — differences, magnitudes, decibels, expressions across signals
  • Bode plots with magnitude and phase in one pane on independent axes, spectrum view for transient, curve families for sweeps, typed axis ranges
  • Envelope decimation keeps multi-million-point transients responsive to pan and zoom, while cursors and FFT always read the full-resolution data
  • Export to CSV, ASCII SPICE raw, SVG, and PNG of the schematic (desktop)

How it is checked

Simulation results are only worth as much as their verification. More than forty complete circuits are run on every build against ngspice through its own shared library, comparing curve by curve within stated tolerances — device curve families, switching converters with reverse recovery, filters, oscillators compared on frequency and amplitude, and behavioral and transfer-function sources compared to a part in a million. Beyond that, more than six hundred tests check individual behavior against closed-form answers where an exact answer exists: filter responses against their algebra, step responses against their exponentials, noise against its integral. A separate torture suite of latches, oscillators and stiff switching converters exercises the operating-point fallback ladder — gmin stepping, source stepping, pseudo-transient continuation — and is scored against ngspice on the same decks; the current build converges several that the reference engine does not.

About this web demo

The demo on this page is the real engine, compiled to WebAssembly. Everything you simulate runs on your own machine and nothing is uploaded. It is deliberately limited compared to the desktop build, and here is exactly how.

In the browser

  • The full solver and every analysis listed above
  • The schematic editor, probing and automatic re-simulation
  • The netlist editor — type or paste a SPICE deck
  • Twenty worked example circuits under the Demos menu
  • The complete waveform viewer, cursors and trace math included

Desktop only

  • Opening and saving files of any kind — browsers do not give the demo filesystem access, so start from a demo or paste a netlist
  • KiCad, LTspice and Verilog import, and watch mode
  • Compiled Verilog-A models through OSDI
  • ngspice as an alternate backend for side-by-side comparison
  • All cores used for sweeps, Monte Carlo, AC and noise; the browser build runs on a single thread, so large sweeps are noticeably slower
  • Exporting results, and settings that persist between sessions

What it does not do

Worth knowing before you invest time, in both builds:

  • No S-parameters, Touchstone files or RF-specific analyses. Frequency-response tables are supported and exact in AC, but a sampled response has no honest time-domain equivalent, so transient falls back to the low-frequency gain and says so.
  • No IBIS. An IBIS model describes I/O buffer behavior for signal-integrity work and is not a circuit model; parts carrying one are skipped with that explanation.
  • Encrypted manufacturer models cannot be simulated — not here and not by any tool without the vendor's key. They are detected and reported rather than failing obscurely.
  • Verilog import is structural only. Gate-level netlists become subcircuits; behavioral RTL must be synthesized first.
  • No electrothermal simulation or self-heating. Temperature is a global sweep parameter with per-device scaling.
  • Gear integration is second-order only. A deck asking for maxord 3 through 6 runs at order 2 with a warning — order 2 is also ngspice's own Gear default, so most decks never notice.
  • PSpice's native Monte Carlo grammar — the .MC/.WCASE analysis cards and DEV/LOT tolerances on .model lines — is not parsed. Spic3y's own .mc and .wcase cards cover the same ground with a different spelling, the same position ngspice is in.

Availability

The web demo above is free to use and needs no account.

The desktop application — with KiCad and LTspice import, watch mode, Verilog-A models, multi-core sweeps and result export — is commercial software, nearing release. Windows first, with Linux and macOS planned. Downloads and licensing will be announced here.

Questions and feedback

If you use the KiCAD-MCP server, Spic3y is the companion piece: it simulates what you just designed, from the same project files, without redrawing anything.